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enpirion ? power datasheet ES1030QI power rail sequencer features ? four enable outputs ? four power good feedback signals ? can be chained with additional devices to achieve >16 sequenced rails ? precise, adjustable qualification time for sequenced supplies (33us to 8. 04 ms) ? aggregate pg signal for the logical and of the individual pg signals ? wide 1.8 v to 5.0 v nominal voltage range ? low power consumptio n ? pb - free/ rohs compliant ? halogen - free ? stqfn - 20 package description the es 1030qi power rail sequencer is a low - power and small - form factor device ideal for establishing the power sequencing pattern in small to large multi - rail power systems (p lease refer to figure 6 ) . the part provides nested sequencing of four outputs per device, wit h the ability to attach additional devices in a sequencing chain for at least 16 outputs. a simple resistor divider establishes a precise qualification time window by determining if each power rail is valid at the correct time. the part uses power good sig nals from the regulators to provide feedback of valid power. separate fault i/o signals and aggregate pg si gnals further enhance the utility of this device. the sequencer is available in a 2mm x 3mm stqfn package, optimal for use in dense systems. pin assignments figure 1 : es 1030qi pin assignments 1 www.altera.com/enpirion
ES1030QI datasheet or dering information part number package markings t ambient rating (c) package description ES1030QI s1030 - 40 to +85 20 - pin ( 2mm x 3mm x 0.55 mm) qfn t&r (3000) evb - ES1030QI qfn e valuation board packing and marking information : www.altera.com/support/reliability/packing/rel - packing - and- marking.html pin description pin name type function 1 vdd pwr supply v oltage 2 nfault_in digital input digital input without schmitt trigger input 3 nfault_o digital output open - drain nmos 4 oe4 digital output push pull 5 oe3 digital output push pull 6 pg3 digital input digital input without schmitt trigger input 7 pg4 digital input digital input without schmitt trigger input 8 acntl analog input/output analog input/output 9 next_o digital output push pull 10 next_in digital input digital input with schmitt trigger input 11 gnd gnd ground 12 pg1 digital input digital input without schmitt trigger input 13 pg2 digital input digital input without schmitt trigger input 14 oe2 digital output push pull 15 oe1 digital output push pull 16 por digital output push pull 17 all_pg digital output push pull 18 ref_o analog input/output analog input/output 19 oe_o digital output push pull 20 en digital input digital input without schmitt trigger input absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter min max units notes v high to gnd - 0.3 7 v open drain output nflt_o . voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperature range - 65 150 c junction temperature -- 150 c electrical characteristics unless otherwise noted : ta = 25c . boldface limits apply over the operating temperature range, t a within - 40c to + 85 c. parameter symbol test conditions min typ max units supply v oltage v dd 1.71 3.3 5.5 v operating t emperature t a ambient temperature with th e chip mounted on a typical pcb - 40 25 85 c 2 www.altera.com/enpirion
ES1030QI parameter symbol test conditions min typ max units quiescent c urrent i q static inputs and outputs ? 300 ? a maximal v oltage a pplied to any pin in h i gh - i mpedance s tate v o ? ? vdd v maximal a verage or dc c urrent 1 i o per each chip side (pin2 - pin10, pin12 - pin20) ? ? 90 ma h igh - level i nput v oltage v ih logic input, at vdd=1.8v 0.98 ? vdd v logic input with schmitt trigger, at vdd=1.8v 1.15 ? vdd logic input, at vdd=3.3v 1.7 5 ? vdd logic input with schmitt trigger, at vdd=3.3v 1.99 ? vdd logic input, at vdd=5.0v 2. 8 8 ? vdd logic input with schmitt trigger, at vdd=5.0v 3. 21 ? vdd low - level input voltage v il logic input, at vdd=1.8v ? ? 0. 77 v logic input with schmitt trigger, at vdd=1.8v ? ? 0. 60 logic input, at vdd=3.3v ? ? 1. 43 logic input with schmitt trigger, at vdd=3.3v ? ? 1.39 logic input, at vdd=5.0v ? ? 2.33 logic input with schmitt trigger, at vdd=5.0v ? ? 2.33 high - level input c urrent i ih logic i nput pins; v in = vdd - 1.0 ? 1.0 a low - level input c urrent i il logic i nput pins; v in = 0v - 1.0 ? 1.0 a high - level output voltage 1 v oh push p ull, i oh = 100ua, at vdd=1.8 v 1.6 7 1.789 ? v push p ull, i oh = 3ma, at vdd=3.3 v 2.7 1 3.1 0 ? push p ull, i oh = 5ma, at vdd=5.0 v 4.1 5 4.7 5 ? l ow - l evel o utput voltage 1 v ol push p ull, i ol = 100ua, at vdd=1.8 v ? 0.0 10 0.01 4 v open d rain, i ol = 100ua, at vdd=1.8 v ? 0.00 7 0.01 2 push p ull, i ol = 3ma, at vdd=3.3 v ? 0.1 48 0. 1 79 open d rain, i ol = 3ma, at vdd=3.3 v ? 0.0 61 0 0 74 push p ull, i ol = 5ma, at vdd=5.0 v ? 0. 189 0.2 25 open d rain, i ol = 5ma, at vdd=5.0 v ? 0. 079 0. 097 h igh - l evel output c urrent 1 i oh push p ull , v oh = v dd - 0.2, at vdd=1.8 v 1. 01 1.7 8 ? ma push pull, v oh = 2.4 v, at vdd=3.3 v 5.5 5 1 0.8 ? push pull, v oh = 2.4 v, at vdd=5.0 v 2 0.1 3 0.0 ? 1 guaranteed by d esign . 3 www.altera.com/enpirion
ES1030QI parameter symbol test conditions min typ max units l ow - l evel output c urrent 1 i ol push p ull, v ol =0.15v, at vdd=1.8 v 1.18 1.6 6 ? ma open d rain, v ol =0.15v, at vdd=1.8 v 2.88 4.08 ? push p ull, v ol =0.4v, at vdd=3.3 v 5.06 7.80 ? open d rain, v ol =0.4v, at vdd=3.3 v 12.0 1 8.9 ? push p ull, v ol =0.4v, at vdd=5.0 v 6.78 1 0.4 ? open d rain, v ol =0.4v, at vdd=5.0 v 1 5.6 25.0 ? internal p ull u p r esistance r pull_up pull up on pins 6, 7, 12, 13 8 5 10 6 1 2 7 k? pull up on pins 3, 20 8 69 10 6 0 1 275 ref_o output v oltage vref (r1+r2)>100k ? 105 0 ? mv delay, actrl / ref_o = 0 tdelay0 ta = 25 c (r1+r2)>100k 0.0 2 8 8 0.03 3 0.03 68 ms - 40c to +85c (r1+r2)>100k 0.02 8 3 0.03 73 delay, actrl / ref_o = 0.5 tdelay0.5 ta = 25 c (r1+r2)>100k 3. 36 3.8 5 4. 32 ms - 40c to +85c (r1+r2)>100k 3.3 6 4.3 9 delay, actrl / ref_o = 1 t d elay1.0 ta = 25 c (r1+r2)>100k 7. 04 8. 0 4 9.06 ms - 40c to +85c (r1+r2)>100k 7. 03 9.19 start - up time t su from vdd rising past 1.6v to first transition on oe1 -- 2.0 2.5 ms 4 www.altera.com/enpirion
ES1030QI f unctional block diagram figure 2 : functional block diagram 5 www.altera.com/enpirion
ES1030QI typical application circuits figure 3 : stand alone operation notes to figure 3 : 1. unused pg pins may be floated or tied to vdd . 2. acntl controls delays based on voltage ratio relative to ref_o : f ull scale delay (actrl at ref_o) is 8. 04ms ; m inimum delay (actrl at gnd) is 3 3 us. 3. for single device, connect next_o to next_in. 4. tie all nfault_x pins of all chained devices together. when fault is detected in any device , the d evice pulls the nfault line low, triggering sequential power down starting with the end device. this is r eleased by en low until fault is cleared. 5. all_pg is a push - pull output for logical and of all pg_ x signals. 6 www.altera.com/enpirion
ES1030QI figure 4 : chained operation notes to figure 4 : 1. connect next_o to next_in on device at end of chain. 2. tie all nfault_x pins of all chained devices together. when fault is detected in any device, the device pulls the nfault line low, triggering sequential power down starting with the end device. this is released by en low until fault is cleared. 3. tie next_o to en of following device. tie next_in to oe_o of following device. application information 7 www.altera.com/enpirion
ES1030QI nested sequencing for many integrated circuits with multiple power supply domains, the manufacturer establishes a prescribed voltage sequencing order for both power - up and power - down . the sequencing order e nsur es the safety of the device and prevent s potentially damaging cu rrents from flowing from one power domain to another through parasitic junctions in the device. the es 1030qi uses the most common pattern of sequencing , nested sequencing , where power domains are activated in a certain order (such as 1 - 2 - 3 - 4 ) and then removed in the reverse order ( 4 - 3 - 2 - 1 ). n ested sequencing is illustrated in the waveform s shown in fig ures 5 through 7 . four - c hannels with qualification window the es 1030qi allows nested sequencing of four power channels per es 1030qi device. after the master enable ( en) signal goes high to start the sequence, each output enable (oex ) signal transitions high in the prescribed 1 - 2 - 3 - 4 order. a resistor divider from the ref_o output to the acntl input pin determines a precision time delay between successive oex outputs. during this time delay , or qualification window , the es 1030qi pauses for a transition of the pgx signal corresponding to the oex signal to indicat e the enabled power supply has a valid output. successive outputs are e nabled with the same qualification window. the power supplies are sequenced down in the reverse order if any of these events are true: 1. negation of the en signal. 2. failure of any pgx to become true within its corresponding qualification window. 3. any other fault (such as from chained es 1030qi parts) introduced into the nfault_in input. this input is negative logic to allow open - drain wired or configurations. precision delay unlike other sequencing solutions which rely on poorly - specified current sources and wide - tolerance capacitors, the es 1030qi generates a precision delay using precision resistors and mixed - signal techniques. an internal reference produces an output voltage which sources 1.0 5 v on the ref_o pin. the vol tage divider you select from ref_o divides th e voltage to any value between 20 mv and 1.0 5 v. the divider impedance (r1+r2) should be kept >100k ohms for accurate delay settings. t he acntl pin samples the divided voltage with an internal analog to digital ( a/d ) converter. the resulting digital value is the divider for an internal clock, result ing in a precision time delay. the delay is scaled to range from 3 3 s to 8. 04 ms according to the formula : tdelay=(n/255)*8.04ms, where n=(vacntl/1.05 v)*255 quantized to 8 - bit values (0- 255) t o limit the potential timing error to less than 20% of the set value, delays for n=5 or less should not be used. the delay time is the same for all intervals between successive outputs , and for both sequence up and sequence down directions. chaining functions use t he es 1030qi in multiple instances to extend the number of power rails sequenced up to at least 16 rails. you can accomplish this by connecting the next_o, next_in, en, oe_o, nfault_o, nfault_in, and all_pg signals as shown in the chaining application circuit in fig ure 4 . this connection extends the behavior of the nested sequencing function to an additional four channels per each es 1030qi added to the chain. e ach es 1030qi has its own time delay generator, and the delay values do not need to be the same for all instances of the part. convenience logic functions the es 1030qi allows additional logic functions to make system application of the part much easier. since the in dividual regulator pgx signals must remain distinct to satisfy the qualification windows during sequencing, an additional signal all_ pg is introduced as the logical and of the individual pgx signals. the nfault_in signal is a negative logic signal driven by the open - drain nfault_o signal, allowing connection to o ther open - drain nfault signals on the same connection. with this connection, other recognized faults in the system can trigger the system to sequence down in an orderly way. the negative logic ( nfault_o ) signal asserts when the qualification windows f or any of the pgx signals fail. in addition to its function as a chaining signal, oe_o going low indicates that the sequence down 8 www.altera.com/enpirion
ES1030QI of all devices connected to this part has completed . voltage l evels and power - on reset ( por ) the internal circuitry of the es 1030qi is functional over the vdd voltage range from 1.71 v to 5.5 v, allowing operation from standard logic voltages from 1.8 v to 5 v. there is an internal initialization time of up to 2.5 ms while the device is preparing for operation. all i/o signa ls on the es 1030qi are in a high - impedance state during the hardware initialization time. the por output indicates by transition to high that the sequencer initialization is complete. the sequencer accept s en inputs before, during, or after internal initi alization, and the outputs begin sequencing in the correct order after the initialization is complete. to avoid additional delay on the first oe, the sequencer should be powered up at least 2.5 ms before the first transition on en. the pgx signal inputs provide internal pull - ups (~100k ohms) to vdd. external pull ups on the pg signal s from the regulator should only be needed if there is significant capacitive loading or leakage current o n the pg signals . logic levels are dependent on the vdd for the es 1030qi as shown in the electrical characteristics table. the nfault_in and next_in signals should have external pull ups to vdd . transitions on the pgx, nfault_in, and next_in signals are ignored during the initialization period. the oex and all_pg output drive signals are push - pull active drivers after initialization. therefore, the output logic drive level is the same as the vdd supply to the es 1030qi . functional ity waveforms waveform definitions for figures 5 to 9 wave pin d0 pin 20 (en) d1 pin 15 (oe1) d2 pin 14 (oe2) d3 pin 5 (oe3) d4 pin 4 (oe4) d5 pin 12 (pg1) d6 pin 13 (pg2) d7 pin 6 (pg3) d8 pin 7 (pg4) d9 pin 17 (all_pg) d10 pin 3 (nfault_o) channel 1 ( yellow) pin 8 (acntl) 9 www.altera.com/enpirion
ES1030QI figure 5 : normal operation, acntl = 0 mv figure 6: normal operation, acntl = 500 mv figure 7: normal operation, acntl = 1000 mv 10 www.altera.com/enpirion
ES1030QI figure 8 : fault: no response from pg4 figure 9 : fault on pg4 waveform definitions for figures 1 0 to 1 2 wave pin d0 pin 20 (en ? chip 1 ) d1 pin 15 (oe1 ? chip 1 ) d2 pin 14 (oe2 ? chip 1 ) d3 pin 5 (oe3 ? chip 1 ) d4 pin 4 (oe4 ? chip 1 ) d5 pin 1 5 ( oe 1 ? chip 2 ) d6 pin 1 4 ( oe 2 ? chip 2 ) d7 pin 5 ( oe 3 ? chip 2 ) d8 pin 4 ( oe 4 ? chip 2 ) d9 pin 3 (nfault_o) d10 pin 16 (por) d11 pin 7 (pg4 ? chip 2) channel 1 ( yellow) pin 1 ( vdd ) channel 1 ( blue) pin 8 (acntl) 11 www.altera.com/enpirion
ES1030QI figure 1 0 : chaining example ? no response from pg4 (chip 2) figure 1 1 : chaining example ? fault on pg4 (chip 2) figure 1 2 : en activated during initialization package information s 1030 ddlll crr part code date code assembly site code lot code revision code figure 1 3 : package top marking 12 www.altera.com/enpirion
ES1030QI figure 1 4 : package drawing and dimensions (20 lead stqfn package jedec mo - 220, variation wece) tape and reel specification package type no. of pins nominal package size (mm) max units reel and hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch stqfn 20l 2x3mm 0.4p green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm l ength (mm) p ocket btm w idth (mm) p ocket d epth (mm) i ndex hole p itch (mm) p ocket p itch (mm) index hole d iameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) t ape width (mm) a0 b0 k0 p0 p1 d0 e f w stqfn 20l 2x3mm 0.4p green 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 13 www.altera.com/enpirion
ES1030QI figure 15 : carrier tape drawing and dimensions recommended reflow soldering profile please see the latest revision of ipc/jedec j - std - 020 for the reflow profile based on a package volume of 3.3 mm 3 (nominal). for more information, visit www.jedec.org . document revision history date document version changes april 2015 2.0 electrical characteristics values, applications text, figure s 10 - 12 waveform labels , figures 3 - 4 febr uary 2015 1.0 initial release. contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 - 544 - 7000 www.altera.com ? 2015 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark offi ce and in o ther countries. all other words and logos identified as trademarks or service marks are the property of their respective holders a s described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specific ations in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera ass umes no responsibility or liability arising out of the application or use of any information, pr oduct, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published informatio n and before placing orders for products or services. 14 www.altera.com/enpirion

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